Multicore Test Based Built In Self-Test Architecture Using Majority Logic

Embedded cores are now commonplace in large system-on-chip designs. However, since embedded cores are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. Testaccess architecture, also referred to as a test-access mechanism (TAM), provides on-chip test data transport. Now days, multi core processor consists of more number of complex digital architecture. This architecture is used for many applications and to improve the application performance level. But it has some problem due to circuit complexity level. Existing work is to modify the test pattern generation logic using preselect logic function. The existing work is pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the design for testability based circuit test pattern generators. Proposed system is to design a multi core parallel testing architecture using majority logic technique. This technique is used to test all internal cores in parallel form. This work is to implement the test pattern creation and to apply the scan chain process. This process is to analysis the separate core internal architecture output result values. The proposed system is to improve the TAM system performance level and to reduce the power consumption level also. The proposed system is used to increase the test pattern generation process. Index Terms – Test access mechanism (TAM), system-on-chip (SoC), automatic test pattern generation (ATPG), automatic test equipment (ATE), preselected toggling (PRESTO) and design for testability (DFT).